In general, a semiconductor chip is required to temporally synchronize signals of inside and outside of the chip in order to accurately exchange the signals with an external device. In such synchronization, an internal clock whose transition time is accurately controlled is generated so that a constant timing relationship with a transition time of a clock (or a strobe, it is mentioned as “clock” in the present application with no distinction made) inputted from the outside of the semiconductor chip is maintained, and usage of this chip internal clock to retrieve the signal is widely practiced. Now, with respect to such phase synchronous circuit, there exists a conventional technique as mentioned below.
In a non-patent document 1, two delay arrays (FDA and BDA) are arranged in parallel in opposite directions, and between thereof, a control circuit MCC is arranged in parallel with the two delay arrays. A load circuit having the same delay time as a clock driver connected to an output of the delay array BDA is pre-designed as a dummy, and is connected to an input of the delay array FDA. This circuit detects a position where a phase is synchronized within the delay array FDA from the delay array FDA and the control circuit MCC, and inputs a clock from the same position of the delay array BDA and transfer the clock in the opposite direction from that of the delay array FDA, so that a fast synchronization is realized in which the phase is synchronized in a delay of two cycles.
Further, in a patent document 1, a ring type coarse adjustment delay device to coarsely adjust a phase and a fine adjustment delay device to finely adjust a phase are provided to configure a ring type and a hierarchical type, so that an entire area of the circuit and the number of gates are reduced. A delay amount is determined such that phases with an external clock and a feedback clock are compared one after another by one phase detector, and from the result, increase and decrease of the delay amount is given to the fine adjustment delay device and the coarse adjustment delay device.
Non-Patent Document 1: IEEE Journal of Solid-state Circuits, Vol. 31, No. 11, November 1996, pp. 1656-1668
Patent Document 1: Japanese Patent Application Laid-Open Publication No. 2003-69424